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phase detector/frequency synthesizer adf4002 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features 400 mhz bandwidth 2.7 v to 3.3 v power supply separate charge pump supply (v p ) allows extended tuning voltage in 3 v systems programmable charge pump currents 3-wire serial interface analog and digital lock detect hardware and software power-down mode 200 mhz phase detector applications clock conditioning clock generation if lo generation general description the adf4002 frequency synthesizer is used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. it consists of a low-noise digital phase frequency detector (pfd), a precision charge pump, a programmable reference divider, and programmable n divider. the 14-bit reference counter (r counter), allows selectable refin frequencies at the pfd input. a complete phase-locked loop (pll) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (vco). in addition, by programming r and n to 1, the part can be used as a stand alone pfd and charge pump. functional block diagram clk data le ref in rf in a rf in b 24-bit input register sd out a v dd dv dd ce agnd dgnd 14-bit r counter r counter latch 22 14 function latch n counter latch 13-bit n counter m3 m2 m1 mux sd out av dd high z muxou t cpgnd r set v p cp phase frequency detector lock detect reference charge pump current setting 1 adf4002 cpi3 cpi2 cpi1 cpi6 cpi5 cpi4 current setting 2 06052-001 figure 1.
adf4002 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 4 absolute maximum ratings ............................................................ 5 thermal characteristics .............................................................. 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 7 theory of operation ........................................................................ 8 reference input section ............................................................... 8 rf input stage ............................................................................... 8 n counter ...................................................................................... 8 r counter ...................................................................................... 8 phase frequency detector (pfd) and charge pump .............. 8 muxout and lock detect .........................................................9 input shift register .......................................................................9 latch maps and descriptions ....................................................... 10 latch summary ........................................................................... 10 reference counter latch map .................................................. 11 n counter latch map ................................................................ 12 function latch map ................................................................... 13 initialization latch map ............................................................ 14 the function latch .................................................................... 15 the initialization latch ............................................................. 16 applications ..................................................................................... 17 very low jitter encode clock for high speed converters ... 17 pfd ............................................................................................... 18 interfacing ................................................................................... 18 pcb design guidelines for chip scale package .................... 18 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 21 revision history 4/06revision 0: initial version
adf4002 rev. 0 | page 3 of 24 specifications av dd = dv dd = 3 v 10%, av dd v p 5.5 v, agnd = dgnd = cpgnd = 0 v, r set = 5.1 k, dbm referred to 50 , t a = t max to t min , unless otherwise noted. table 1. b version 1 parameter min typ max unit test conditions/comments rf characteristics see figure 12 for input circuit rf input sensitivity ?10 0 dbm rf input frequency (rf in ) 5 400 mhz for rf in < 5 mhz, ensure slew rate (sr) > 4 v/s refin characteristics refin input frequency 20 300 mhz for refin < 20 mhz, ensure sr > 50 v/s refin input sensitivity 2 0.8 v dd v p-p biased at av dd /2 3 refin input capacitance 10 pf refin input current 100 a phase detector phase detector frequency 4 200 mhz charge pump programmable, see figure 19 i cp sink/source high value 5 ma with r set = 5.1 k low value 625 a absolute accuracy 2.5 % with r set = 5.1 k r set range 3.0 11 k see figure 19 i cp three-state leakage 1 na t a = 25c i cp vs. v cp 1.5 % 0.5 v v cp v p C 0.5 v sink and source current matching 2 % 0.5 v v cp v p C 0.5 v i cp vs. temperature 2 % v cp = v p /2 logic inputs v ih , input high voltage 1.4 v v il , input low voltage 0.6 v i inh , i inl , input current 1 a c in , input capacitance 10 pf logic outputs v oh , output high voltage 1.4 v open-drain output chosen, 1 k pull-up resistor to 1.8 v v oh , output high voltage v dd C 0.4 v cmos output chosen i oh 100 a v ol , output low voltage 0.4 v i ol = 500 a power supplies av dd 2.7 3.3 v dv dd av dd v p av dd 5.5 v av dd v p 5.5 v i dd 5 (ai dd dd + di ) 5.0 6.0 ma i p 0.4 ma t a = 25c power-down mode 1 a ai dd + di dd noise characteristics normalized phase noise floor 6 C222 dbc/hz 1 operating temperature range (b version) is C40c to +85c. 2 av dd = dv dd = 3 v. 3 ac coupling ensures av dd /2 bias. 4 guaranteed by design. sample tested to ensure compliance. use of the pfd at frequencies abov e 104 mhz requires the minimum ant ibacklash pulse width enabled. 5 t a = 25c; av dd = dv dd = 3 v; rf in = 350 mhz. the current for any other setup (25c, 3.0 v) in ma is given by 2.35 + 0.0046 (refin) + 0.0062 (rf), rf frequency a nd refin frequency in mhz. 6 the normalized phase noise floor is estimated by measuring the in-band phase no ise at the output of the vco and subtracting 20 logn (where n is the n divider value) and 10logf pfd . pn synth = pn tot C 10logf pfd C 20logn. all phase noise measurements were performed with an agilent e5500 phas e noise test system, using the eval- adf4002eb1 and the hp8644b as the pll reference.
adf4002 rev. 0 | page 4 of 24 timing characteristics av dd = dv dd = 3 v 10%, av dd v p 5.5 v, agnd = dgnd = cpgnd = 0 v, r set = 5.1 k, dbm referred to 50 , t a = t max to t min , unless otherwise noted. 1 table 2. parameter limit (b version) 2 unit test conditions/comments t 1 10 ns min data to clk setup time t 2 10 ns min data to clk hold time t 3 25 ns min clk high duration t 4 25 ns min clk low duration t 5 10 ns min clk to le setup time t 6 20 ns min le pulse width 1 guaranteed by design, but not production tested. 2 operating temperature range (b version) is C40c to +85c. timing diagram clk db22 db2 data le t 1 le db23 (msb) t 2 db1 (control bit c2) db0 (lsb) (control bit c1) t 3 t 4 t 6 t 5 06052-022 figure 2. timing diagram
adf4002 rev. 0 | page 5 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to gnd 1 C0.3 v to +3.6 v av dd to dv dd C0.3 v to +0.3 v v p to gnd C0.3 v to +5.8 v v p to av dd C0.3 v to +5.8 v digital i/o voltage to gnd C0.3 v to vdd + 0.3 v analog i/o voltage to gnd C0.3 v to v p + 0.3 v refin, rf in a, rf in b to gnd C0.3 v to vdd + 0.3 v operating temperature range industrial (b version) C40c to +85c storage temperature range C65c to +125c maximum junction temperature 150c lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c transistor count cmos 6425 bipolar 303 1 gnd = agnd = dgnd = 0 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of <2 kv, and it is esd sensitive. proper precautions should be taken for handling and assembly. thermal characteristics table 4. thermal impedance package type ja unit tssop 150.4 c/w lfcsp_vq 122 c/w esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
adf4002 rev. 0 | page 6 of 24 pin configurations and function descriptions r set cp cpgnd agnd muxout le data clk ce dgnd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 rf in b rf in a av dd ref in v p dv dd adf4002 top view (not to scale) 06052-002 pin 1 indicator figure 3. tssop (top view) 15 muxout 14 le 13 data 12 clk cpgnd 1 agnd 2 agnd 3 20 cp 11 ce 6 7 8 dgnd 9 dgnd 10 4 5 19 18 17 16 rf in b rf in a r set v p dv dd dv dd av dd av dd ref in pin 1 indicator adf4002 top view (not to scale) 0 6052-003 figure 4. lfcsp_vq (top view) table 5. pin function descriptions pin no. tssop lfcsp_vq mnemonic description 1 19 r set connecting a resistor between this pin and cpgnd sets the maximum charge pump output current. the nominal voltage potential at the r set pin is 0.66 v. the relationship between i cp and r set is set maxcp r i = where r set = 5.1 k and i cp max = 5 ma. 2 20 cp charge pump output. when enabled, this provides i cp to the external loop filter that, in turn, drives the external vco. 3 1 cpgnd charge pump ground. this is th e ground return path for the charge pump. 4 2, 3 agnd analog ground. this is the ground return path of the rf input. 5 4 rf in b complementary input to the rf input. this point mu st be decoupled to the ground plane with a small bypass capacitor, typically 100 pf. see figure 12 . 6 5 rf in a input to the rf input. this small signal input is ac-coupled to the external vco. 7 6, 7 av dd analog power supply. this can range from 2.7 v to 3. 3 v. decoupling capacitors to the analog ground plane should be placed as close as possible to the av dd pin. av dd must be the same value as dv dd . 8 8 ref in reference input. this is a cmos in put with a nominal threshold of v dd /2 and a dc equivalent input resistance of 100 k. see figure 11 . this input can be driven from a ttl or cmos crystal oscillator or it can be ac-coupled. 9 9, 10 dgnd digital ground. 10 11 ce chip enable. a logic low on this pin powers down the device and puts the charge pump output into three-state mode. taking this pin high powers up the device, depending on the status of the power- down bit f2. 11 12 clk serial clock input. this serial clock is used to cloc k in the serial data to the registers. the data is latched into the 24-bit shift register on the clk ri sing edge. this input is a high impedance cmos input. 12 13 data serial data input. the serial data is loaded msb-first with the two lsbs being the control bits. this input is a high impedance cmos input. 13 14 le load enable, cmos input. when le goes high, the data stored in the shift registers is loaded into one of the four latches; the latch is selected using the control bits. 14 15 muxout this multiplexer output allows either the lock detect, the scaled rf, or the scaled reference frequency to be accessed externally. 15 16, 17 dv dd digital power supply. this can range from 2.7 v to 3. 3 v. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. dv dd must be the same value as av dd . 16 18 v p charge pump power supply. this should be greater than or equal to v dd . in systems where v dd is 3 v, it can be set to 5.5 v and used to drive a vco with a tuning range of up to 5 v.
adf4002 rev. 0 | page 7 of 24 typical performance characteristics 0 ?5 ?10 ?15 ?20 ?25 ?30 ?40 ?35 0 100 200 300 400 500 600 06052-027 power (dbm) frequency (mhz) ?40c +85c +25c figure 5. rf input sensitivity 012345 10 9 68 7 06052-026 power (dbm) frequency (mhz) 0 ?5 ?10 ?15 ?20 ?25 ?40c +25c +85c figure 6. rf input sensitivity, low frequency ? 70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 1k 10k 100k 1m 10m 06052-031 phase noise (dbc/hz) frequency offset (hz) rms noise = 0.07 degrees figure 7. integrated phase noise (400 mhz, 1 mhz, 50 khz) ? 70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 1k 10k 100k 1m 10m 06052-032 power (dbc/hz) frequency offset (hz) rms noise = 0.03 degrees figure 8. integrated phase noise (400 mhz, pfd = 200 mhz, 50 khz) ? 130 ?135 ?140 ?145 ?155 ?160 ?165 ?170 ?175 ?180 100k 1m 10m 100m 1g 06052-033 phase noise (dbc/hz) pfd frequency (hz) figure 9. phase noise (referred to cp output) vs. pfd frequency 06052-030 ref ?4dbm samp log 10db/ attn 10db vbw 20khz mkr1 1.000 mhz ?94.5dbc center 399.995mhz res bw 20khz span 2.2mhz sweep 21ms (601pts) ?94.5dbc 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?90 ?100 ?80 1 1r figure 10. reference spurs (400 mhz, 1 mhz, 7 khz)
adf4002 rev. 0 | page 8 of 24 theory of operation reference input section the reference input stage is shown in figure 11 . sw1 and sw2 are normally closed switches. sw3 is normally open. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. 100k ? nc ref in nc no sw1 sw2 buffer sw3 to r counter power-down control 06052-013 figure 11. reference input stage rf input stage the rf input stage is shown in figure 12 . it is followed by a 2-stage limiting amplifier to generate the cml clock levels needed for the n counter. 500 ? 1.6v 500 ? agnd bias generator rf in a rf in b av dd 06052-014 figure 12. rf input stage n counter the n cmos counter allows a wide ranging division ratio in the pll feedback counter. division ratios from 1 to 8191 are allowed. n and r relationship the n counter makes it possible to generate output frequencies that are spaced only by the reference frequency divided by r. the equation for the vco frequency is r refin f n vco f = where: f vco is the output frequency of external voltage controlled oscillator (vco). n is the preset divide ratio of binary 13-bit counter (1 to 8191). f refin is the external reference frequency oscillator. to pfd from rf input stage from n counter latch 13-bit n counter 06052-021 figure 13. n counter r counter the 14-bit r counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed. phase frequency detector (pfd) and charge pump the pfd takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 14 is a simplified schematic. the pfd includes a programmable delay element that controls the width of the antibacklash pulse. this pulse ensures that there is no dead zone in the pfd transfer function, and minimizes phase noise and reference spurs. two bits in the reference counter latch (abp2 and abp1) control the width of the pulse. see figure 17 for details. the smallest antibacklash pulse width (1.3 ns) should be used if the desired pfd exceeds 104 mhz.
adf4002 rev. 0 | page 9 of 24 hi hi d1 d2 q1 q2 clr1 clr2 cp u1 u2 up down abp2 abp1 cpgnd u3 r divider programmable delay n divider v p charge pump 06052-023 figure 14. pfd simplified schematic and timing (in lock) muxout and lock detect the output multiplexer on the adf4002 allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m2, and m1 in the function latch. figure 19 shows the full truth table. figure 15 shows the muxout section in block diagram form. dgnd dv dd control mux analog lock detect digital lock detect r counter output n counter output sdout muxout 06052-024 figure 15. muxout circuit lock detect muxout can be programmed for two types of lock detect: digital lock detect and analog lock detect. digital lock detect is active high. when ldp in the r counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector (pd) cycles is less than 15 ns. with ldp set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. it stays set at high until a phase error of greater than 25 ns is detected on any subsequent pd cycle. for pfd frequencies greater than 10 mhz, analog lock detect is more accurate because of the smaller pulse widths. the n-channel, open-drain, analog lock detect should be operated with an external pull-up resistor of 10 k nominal. when lock has been detected this output is high with narrow, low-going pulses. input shift register the adf4002 digital section includes a 24-bit input shift register, a 14-bit r counter, and a 13-bit n counter. data is clocked into the 24-bit shift register on each rising edge of clk. the data is clocked in msb-first. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2, c1) in the shift register. these are the two lsbs, db1 and db0, as shown in the timing diagram (see figure 2 ). table 6 provides the truth table for these bits. figure 16 shows a summary of how the latches are programmed. table 6. c2, c1 truth table control bits c2 c1 data latch 0 0 r counter 0 1 n counter 1 0 function latch 1 1 initialization latch
adf4002 rev. 0 | page 10 of 24 latch maps and descriptions latch summary db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2 r3r4r5 r6 r7 r8r9 r10 r11 r12 r13 r14 abp1 abp2 t1 t2 ldp db21 db22 db23 00 x db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) b1 b2 b3b4b5b6 b7b8 b9 b10 b11 b12 b13 xxxxxx db21 db22 db23 g1 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) f1 pd1 m1m2m3 f3 x xc p i 1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4 f5 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 d b 8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) f1 pd1 m1m2m3 f3 x xc p i 1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4f5 reference counter l a tch reserved lock detect precision test mode bits anti- backlash width 14-bit reference counter control bits reserved 13-bit n counter reserved control bits n counter latch cp gain function latch power- down 2 current setting 2 current setting 1 timer counter control fastlock mode fastlock enable cp three- state pd polarity muxout control power- down 1 counter reset control bits reserved power- down 2 current setting 2 current setting 1 timer counter control fastlock mode fastlock enable cp three- state pd polarity muxout control power- down 1 counter reset control bits initialization latch reserved 06052-015 figure 16. latch summary
adf4002 rev. 0 | page 11 of 24 reference counter latch map ldp 0 1 abp2 abp1 0 0 2.9ns 0 1 1.3ns 1 0 6.0ns 1 1 2.9ns r14 r13 r12 .......... r3 r2 r1 0 0 0 .......... 0 0 1 1 0 0 0 .......... 0 1 0 2 0 0 0 .......... 0 1 1 3 0 0 0 .......... 1 0 0 4 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 1 6380 1 1 1 .......... 1 0 1 1 6381 1 1 1 .......... 1 1 0 1 6382 1 1 1 .......... 1 1 1 1 6383 x = don?t care db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1r2r3r4 r5 r6r7r8 r9 r10 r11 r12 r13 r14 abp1 abp2 t1 t2 ldp db21 db22 db23 00 x reserved lock detect precision test mode bits anti- backlash width 14-bit reference counter control bits divide ratio antibacklash pulsewidth test mode bits should be set to 00 for normal operation. operation three consecutive cycles of phase delay less than 15ns must occur before lock detect is set. five consecutive cycles of phase delay less than 15ns must occur before lock detect is set. both of these bits must be set to 0 for normal operation. 06052-025 figure 17. reference counter latch map
adf4002 rev. 0 | page 12 of 24 n counter latch map db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) b1 b2 b3b4b5 b6 b7 b8b9 b10 b11 b12 b13 xx xxxx db21 db22 db23 g1 00 0 1 1 0 f4 (function latch) fastlock enable 11 xx n13 n12 n11 n3 n2 n1 0 0 0 .......... 0 0 0 0 0 0 .......... 0 0 1 0 0 0 .......... 0 1 0 0 0 0 .......... 0 1 1 3 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 8188 1 1 1 .......... 1 0 1 8189 1 1 1 .......... 1 1 0 8190 1 1 1 .......... 1 1 1 8191 x = don?t care reserved 13-bit n counter reserved control bits cp gain n counter divide ratio not allowed 1 2 these bits are not used by the device and are don't care bits. operation cp gain charge pump current setting 1 is permanently used. charge pump current setting 2 is permanently used. charge pump current setting 1 is used. charge pump current is switched to setting 2. the time spent in setting 2 is dependent on which fastlock mode is used. see function latch description. these bits are not used by the device and are don't care bits. 06052-016 figure 18. n counter latch map
adf4002 rev. 0 | page 13 of 24 function latch map pd2 pd1 mode 0 x x 1 x0 101 111 cpi6 cpi5 cp14 cpi3 cpi2 cpi1 3k? 5.1k ? 11k ? 000 001 010 011 100 101 110 111 tc4 tc3 tc2 tc1 00003 00017 00101 1 00111 5 01001 9 01012 3 01102 7 01113 1 10003 5 10013 9 10104 3 10114 7 11005 1 11015 5 11105 9 11116 3 f4 0 1 1 m3 m2 m1 000 001 010 011 100 101 110 111 f3 0 1 f2 0 1 f1 0 1 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) f1 pd1 m1 m2 m3 f3 p1p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4 f5 three-state f5 x 0 1 negative positive reserved power- down 2 current setting 2 current setting 1 timer counter control fastlock mode fastlock enable cp three- state muxout control power- down 1 counter reset control bits phase detector polarity counter operation normal r, a, b counters held in reset charge pump output normal fastlock disabled fastlock mode 1 fastlock mode 2 fastlock mode three-state output digital lock detect (active high) n divider output dv dd r divider output n-channe l open-drain lock detect serial data output dgnd output timeout (pfd cycles) i cp (ma) asynchronous power-down normal operation asynchronous power-down synchronous power-down ce pin pd polarity 06052-017 these bits are not used by the device and are don't care bits. 1.088 2.176 3.264 4.352 5.440 6.528 7.616 8.704 0.625 1.250 1.875 2.500 3.125 3.750 4.375 5.000 0.294 0.588 0.882 1.176 1.470 1.764 2.058 2.352 see page 16 figure 19. function latch map
adf4002 rev. 0 | page 14 of 24 initialization latch map pd2 pd1 mode 0 x x 1 x0 101 111 cpi6 cpi5 cp14 cpi3 cpi2 cpi1 3k? 5.1k ? 11k ? 000 001 010 011 100 101 110 111 tc4 tc3 tc2 tc1 00003 00017 00101 1 00111 5 01001 9 01012 3 01102 7 01113 1 10003 5 10013 9 10104 3 10114 7 11005 1 11015 5 11105 9 11116 3 f4 0 1 1 m3 m2 m1 000 001 010 011 100 101 110 111 f3 0 1 f2 0 1 f1 0 1 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) f1 pd1 m1 m2m3 f3 p1p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4 f5 three-state f5 x 0 1 negative positive reserved power- down 2 current setting 2 current setting 1 timer counter control fastlock mode fastlock enable cp three- state muxout control power- down 1 counter reset control bits phase detector polarity counter operation normal r, a, b counters held in reset charge pump output normal fastlock disabled fastlock mode 1 fastlock mode 2 fastlock mode three-state output digital lock detect (active high) n divider output dv dd r divider output n-channe l open-drain lock detect serial data output dgnd output timeout (pfd cycles) i cp (ma) asynchronous power-down normal operation asynchronous power-down synchronous power-down ce pin pd polarity 06052-036 these bits are not used by the device and are don't care bits. 1.088 2.176 3.264 4.352 5.440 6.528 7.616 8.704 0.625 1.250 1.875 2.500 3.125 3.750 4.375 5.000 0.294 0.588 0.882 1.176 1.470 1.764 2.058 2.352 see page 16 figure 20. initialization latch map
adf4002 rev. 0 | page 15 of 24 the function latch with c2, c1 set to 1, 0, the on-chip function latch is programmed. figure 19 shows the input data format for programming the function latch. counter reset db2 (f1) is the counter reset bit. when this bit is set to 1, the r counter and the n counters are reset. for normal operation, set this bit to 0. upon powering up, the f1 bit needs to be disabled (set to 0). then, the n counter resumes counting in close alignment with the r counter (the maximum error is one prescaler cycle). power-down db3 (pd1) and db21 (pd2) provide programmable power- down modes. these bits are enabled by the ce pin. when the ce pin is low, the device is immediately disabled regardless of the states of the pd2, pd1 bits. in the programmed asynchronous power-down, the device powers down immediately after latching a 1 into bit pd1, with the condition that bit pd2 has been loaded with a 0. in the programmed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. once the power-down is enabled by writing a 1 into bit pd1 (on condition that a 1 has also been loaded to bit pd2), then the device enters power-down on the occurrence of the next charge pump event. when a power-down is activated (either in synchronous or asynchronous mode, including a ce pin activated power- down), the following events occur: ? all active dc current paths are removed. ? the r, n, and timeout counters are forced to their load- state conditions. ? the charge pump is forced into three-state mode. ? the digital lock detect circuitry is reset. ? the rfin input is debiased. ? the reference input buffer circuitry is disabled. ? the input register remains active and capable of loading and latching data. muxout control the on-chip multiplexer is controlled by m3, m2, and m1 on the adf4002. figure 19 shows the truth table. fastlock enable bit db9 of the function latch is the fastlock enable bit. only when this is 1 is fastlock enabled. fastlock mode bit db10 of the function latch is the fastlock mode bit. when fastlock is enabled, this bit determines the fastlock mode to be used. if the fastlock mode bit is 0, then fastlock mode 1 is selected, and if the fastlock mode bit is 1, then fastlock mode 2 is selected. fastlock mode 1 in this mode, the charge pump current is switched to the contents of current setting 2. the device enters fastlock by having a 1 written to the cp gain bit in the n counter latch. the device exits fastlock by having a 0 written to the cp gain bit in the ab counter latch. fastlock mode 2 in this mode, the charge pump current is switched to the contents of current setting 2. the device enters fastlock by having a 1 written to the cp gain bit in the n counter latch. the device exits fastlock under the control of the timer counter. after the timeout period determined by the value in tc4 to tc1, the cp gain bit in the n counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. see figure 19 for the timeout periods. timer counter control the user has the option of programming two charge pump currents. the intent is to use the current setting 1 when the rf output is stable and the system is in a static state. current setting 2 is meant to be used when the system is dynamic and in a state of change, that is, when a new output frequency is programmed. the normal sequence of events is as follows: the user initially decides the referred charge pump currents. for example, the choice can be 2.5 ma as current setting 1 and 5 ma as current setting 2. at the same time, the decision must be made as to how long the secondary current is to stay active before reverting to the primary current. this is controlled by timer counter control bit db14 to timer counter control bit db11 (tc4 to tc1) in the function latch. see figure 19 for the truth table. to program a new output frequency, simply program the n counter latch with a new value for n. at the same time, the cp gain bit can be set to 1. this sets the charge pump with the value in cpi6 to cpi4 for a period of time determined by tc4 to tc1. when this time is up, the charge pump current reverts to the value set by cpi3 to cpi1. at the same time, the cp gain bit in the n counter latch is reset to 0 and is ready for the next time that the user wishes to change the frequency. note that there is an enable feature on the timer counter. it is enabled when fastlock mode 2 is chosen by setting the fastlock mode bit db10 in the function latch to 1.
adf4002 rev. 0 | page 16 of 24 charge pump currents cpi3, cpi2, and cpi1 program current setting 1 for the charge pump. cpi6, cpi5, and cpi4 program current setting 2 for the charge pump. see figure 19 for the truth table. pd polarity this bit sets the phase detector polarity bit (see figure 19 ). cp three-state this bit controls the cp output pin. setting the bit high, puts the cp output into three-state. with the bit set low, the cp output is enabled. the initialization latch the initialization latch is programmed when c2, c1 = 1, 1. this is essentially the same as the function latch (programmed when c2, c1 = 1, 0). however, when the initialization latch is programmed there is an additional internal reset pulse applied to the r and n counters. this pulse ensures that the n counter is at load point when the n counter data is latched and the device begins counting in close phase alignment. if the latch is programmed for synchronous power-down (ce pin is high; pd1 bit is high; and pd2 bit is low), the internal pulse also triggers this power-down. the prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse, thereby maintaining close phase alignment when counting resumes. when the first n counter data is latched after initialization, the internal reset pulse is reactivated. however, successive ab counter loads after this do not trigger the internal reset pulse. device programming after initial power-up after initially powering up the device, there are three ways to program the device. initialization latch method 1. apply v dd . 2. program the initialization latch (11 in two lsbs of input word). make sure that the f1 bit is programmed to 0. 3. conduct a function latch load (10 in two lsbs of the control word). make sure that the f1 bit is programmed to 0. 4. perform an r load (00 in two lsbs). 5. perform an n load (01 in two lsbs). when the initialization latch is loaded, the following occurs: ? the function latch contents are loaded. ? an internal pulse resets the r, n, and timeout counters to load-state conditions and three-states the charge pump. note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. ? latching the first n counter data after the initialization word activates the same internal reset pulse. successive n loads do not trigger the internal reset pulse unless there is another initi alization. ce pin method 1. apply v dd . 2. bring ce low to put the device into power-down. this is an asynchronous power-down because it happens immediately. 3. program the function latch (10). 4. program the r counter latch (00). 5. program the n counter latch (01). 6. bring ce high to take the device out of power-down. the r and n counters resume counting in close alignment. note that after ce goes high, a duration of 1 s can be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. ce can be used to power the device up and down to check for channel activity. the input register does not need to be reprogrammed each time the device is disabled and enabled, as long as it has been programmed at least once after v dd was initially applied. counter reset method 1. apply v dd . 2. do a function latch load (10 in two lsbs). as part of this step, load 1 to the f1 bit. this enables the counter reset. 3. perform an r counter load (00 in two lsbs). 4. perform an n counter load (01 in two lsbs). 5. do a function latch load (10 in two lsbs). as part of this step, load 0 to the f1 bit. this disables the counter reset. this sequence provides the same close alignment as the initialization method. it offers direct control over the internal reset. note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down.
adf4002 rev. 0 | page 17 of 24 applications very low jitter encode clock for high speed converters figure 21 shows the adf4002 with a vcxo to provide the encode clock for a high speed analog-to-digital converter (adc). the converter used in this application is an ad9215-80 , a 12-bit converter that accepts up to an 80 mhz encode clock. to realize a stable low jitter clock, use a 77.76 mhz, narrow band vcxo. this example assumes a 19.44 mhz reference clock. to minimize the phase noise contribution of the adf4002, the smallest multiplication factor of 4 is used. thus, the r divider is programmed to 1, and the n divider is programmed to 4. the charge pump output of the adf4002 (pin 2) drives the loop filter. the loop filter bandwidth is optimized for the best possible rms jitter, a key factor in the signal-to-noise ratio (snr) of the adc. too narrow a bandwidth allows the vcxo noise to dominate at small offsets from the carrier frequency. too wide a bandwidth allows the adf4002 noise to dominate at offsets where the vcxo noise is lower than the adf4002 noise. thus, the intersection of the vcxo noise and the adf4002 in- band noise is chosen as the optimum loop filter bandwidth. the design of the loop filter uses the adisimpll (version 3.0) and is available as a free download from www.analog.com/pll . the rms jitter is measured at <1.2 ps. this level is lower than the maximum allowable 6 ps rms required to ensure the theoretical snr performance of 59 db for this converter. the setup shown in figure 21 using the adf4002, ad9215, and hsc-adc-evala-sc, allows the user to quickly and effectively determine the suitability of the converter and encode clock. the spi? interface is used to control the adf4002, and the usb interface helps control the operation of the ad9215- 80. the controller board sends back fft information to the pc that, if using an adc analyzer, provides all conversion results from the adc. vcxo: 77.76mhz hc-adc-evala-sc pc usb tcxo: 19.44mhz encode clock a in adf4002 n = 4 pd r = 1 spi agilent: 500khz, 1.8v p-p 06052-034 ad9215-80 figure 21. adf4002 as encode clock
adf4002 rev. 0 | page 18 of 24 pfd as the adf4002 permits both r and n counters to be programmed to 1, the part can effectively be used as a stand alone pfd and charge pump. this is particularly useful in either a clock cleaning application or a high performance lo. addi- tionally, the very low normalized phase noise floor (?222 dbc/hz) enables very low in-band phase noise levels. it is possible to operate the pfd up to a maximum frequency of 200 mhz. in figure 22 , the reference frequency equals the pfd, therefore, r = 1. the charge pump output integrates into a stable control voltage for the vcxo, and the output from the vcxo is divided down to the desired pfd frequency using an external divider. 06052-035 8 2 16 15 7 6 5 943 1 ref in ref in r set rf in a rf in b av dd dv dd cpgnd agnd dgnd v dd v p v p ce adf4002 decoupling capacitors and interface signals have been omitted from the diagram in the interests of greater clarity. 100pf 100pf 51 ? 10k ? loop filter gnd vco or vcxo v cc gnd external prescaler 18 ? 18 ? 18 ? 100pf 100pf rf out v cc v cc figure 22. adf4002 as a pfd interfacing the adf4002 has a simple spi-compatible serial interface for writing to the device. clk, data, and le control the data transfer. when the latch enable (pin le) goes high, the 24 bits that have been clocked into the input register on each rising edge of clk are transferred to the appropriate latch. for more information, see figure 2 for the timing diagram and table 6 for the latch truth table. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible for the device is 833 khz, or one update every 1.2 s. this is certainly more than adequate for systems that have typical lock times in hundreds of microseconds. aduc812 interface figure 23 shows the interface between the adf4002 and the aduc812 microconverter?. since the aduc812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf4002 needs a 24-bit word. this is accomplished by writing three, 8-bit bytes from the microconverter to the device. when the third byte has been written, bring the le input high to complete the transfer. on first applying power to the adf4002, it needs four writes (one each to the initialization latch, function latch, r counter latch, and n counter latch) for the output to become active. i/o port lines on the aduc812 are also used to control power- down (ce input) and to detect lock (muxout configured as lock detect and polled by the port input). when operating in the spi master mode, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed is 166 khz. clk data le ce muxout (lock detect) mosi sclock i/o ports aduc812 adf4002 06052-019 figure 23. aduc812 to adf4002 interface adsp2181 interface figure 24 shows the interface between the adf4002 and the adsp21xx digital signal processor. the adf4002 needs a 24-bit serial word for each latch write. the easiest way to accomplish this using the adsp21xx family is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. set up the word length for 8 bits and use three memory locations for each 24-bit word. to program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. clk data le ce muxout (lock detect) adsp21xx adf4002 dt sclk i/o flags tfs 06052-020 figure 24. adsp-21xx to adf4002 interface pcb design guidelines for chip scale package the lands on the lead frame chip scale package (cp-20-1) are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this ensures that the solder joint size is maximized.
adf4002 rev. 0 | page 19 of 24 the bottom of the lead frame chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. on the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. this ensures that shorting is avoided. thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm and the via barrel should be plated with 1 oz. copper to plug the via. the user should connect the printed circuit board thermal pad to agnd.
adf4002 rev. 0 | page 20 of 24 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 25. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 1 20 5 6 11 16 15 10 2.25 2.10 sq 1.95 0.75 0.55 0.35 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicato r top view 3.75 bcs sq 4.00 bsc sq coplanarity 0.08 0.60 max 0.60 max 0.25 min compliant to jedec standards mo-220-vggd-1 pin 1 indicator figure 26. 20-lead lead frame chip scale package [lfcsp_vq] (cp-20-1) dimensions shown in millimeters
adf4002 rev. 0 | page 21 of 24 ordering guide model temperature range package description package option adf4002bruz 1 C40c to +85c 16-lead tssop ru-16 adf4002bruzCrl 1 C40c to +85c 16-lead tssop ru-16 adf4002bruzCrl7 1 C40c to +85c 16-lead tssop ru-16 adf4002bcpz 1 C40c to +85c 20-lead lfcsp_vq cp-20-1 adf4002bcpzCrl 1 C40c to +85c 20-lead lfcsp_vq cp-20-1 adf4002bcpzCrl7 1 C40c to +85c 20-lead lfcsp_vq cp-20-1 eval-adf4002eb1 evaluation board eval-adf411xeb1 evaluation board 1 z = pb-free part.
adf4002 rev. 0 | page 22 of 24 notes
adf4002 rev. 0 | page 23 of 24 notes
adf4002 rev. 0 | page 24 of 24 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06052-0-4/06(0)

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